An SRAM (Static Random Access Memory), which is a semiconductor memory device, has the advantage of very low power consumption, because it can store data without requiring a regular refresh operation as used in a DRAM (Dynamic Random Access Memory).
However, in the case of an SRAM that performs no regular refresh operation, the retention characteristic is deteriorated due to leakage currents generated during standby, as the case may be. Conventionally, in consideration of this problem, the power supply voltage (VDD) inside the cell array is set lower so that the leakage currents in memory cells can be suppressed. However, according to this method, it is difficult to stabilize the VDD thus lowered, with respect to variations in process conditions, power supply voltage, and/or process temperature (which will be referred to as “PVT” (Process/Voltage/Temperature), hereinafter). Thus, there is a case that the retention characteristic is deteriorated due to PVT variations.